D flip flop verilog HDL code

module dflipflop( q,qbar,d,clk,clear);
input d,clk,clear;
output q,qbar;
wire s,sbar,r,rbar,cbar;
assign cbar= ~clear;
assign sbar = ~(rbar & s),
  s = ~(sbar & cbar & (~clk)),
  r = ~(rbar & (~clk) & s),
  rbar = ~(r & cbar & d);
assign q = ~(s & qbar),
  qbar = ~(q & r & cbar);
endmodule

module dflipflop0();
wire q0,qbar0;
reg d0,clk0,clear0;
initial
begin
clk0=1;
clear0=1;
d0=1;

#10 clk0=1;
#00 clear0=0;
#00 d0=1;

#20 clk0=0;
#00 clear0=0;
#00 d0=1;

#30 clk0=0;
#00 clear0=1;
#00 d0=1;
end
dflipflop s(.clear(clear0),.clk(clk0),.q(q0),.qbar(qbar0),.d(d0));
endmodule